1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to a semiconductor memory device in which power consumption is reduced when an input/output line pair (referred to as an IO line pair hereinafter) is equalized.
2. Description of the Background Art
In a semiconductor memory device having a larger storage capacity, a memory cell array is often divided into a plurality of blocks and, in each of these blocks, circuit operations for data writing and data reading are carried out, with a view to reducing power consumption and avoiding an increase of an access time.
FIG. 7 is a schematic block diagram showing a whole configuration of a DRAM (Dynamic Random Access Memory) having a block-divided structure which is one example of the semiconductor memory devices. Referring to FIG. 7, the whole configuration in the operation of the DRAM will be hereinafter described.
A memory cell array 1 is divided into eight blocks 101-108.
FIG. 8 is a circuit diagram showing a specific structure of each of blocks 101-108. These blocks 101-108 have the same structure, and in FIG. 8, only a structure of one block is shown as a representative.
Referring to FIG. 8, each block includes a plurality of memory cells MC arranged in a matrix of a plurality of rows and columns, a plurality of word lines WL corresponding to these plural rows, and a plurality of bit lines BL1, BL2 corresponding to these plural columns, as a main portion.
Each memory cell MC includes a MOS transistor Tr having a gate connected to word line WL corresponding to the row in which the memory cell is arranged and a drain connected to bit line BL1 or BL2 provided corresponding to the row in which the memory cell is arranged, and a capacitor C connected between the transistor Tr and a low potential source such as a cell plate. Different word lines WL are connected to a memory cell MC connected to one of two adjacent bit lines BL1 and BL2 and a memory cell MC connected to the other bit line, respectively. Two adjacent bit lines BL1 and BL2 forms one bit line pair BL.
A state in which capacitor C is charged and a state in which capacitor C is discharged respectively correspond to a state in which a stored data of memory cell MC is "1" and a state in which the data is "0".
Each block further includes sense amplifiers 14 provided corresponding to all bit line pairs BL, respectively, paired input/output lines 201, 202, a transfer gate 15 provided between the input/output line pair and respective sense amplifiers 14.
Transfer gate 15 includes two MOS transistors 151, 152 corresponding to each sense amplifier 14.
Each transistor 151 is connected between a corresponding sense amplifier 14 and IO line 201, and each transistor 152 is connected between corresponding sense amplifier 14 and IO line 202. That is, one pair of transistors 500 is connected to each sense amplifier 14 to electrically connect the sense amplifier to two data lines 201, 202.
Each block further includes a row decoder 12 controlling a potential of each word line WL and a column decoder 13 controlling transfer gate 15.
A gate potential of two transistors 151, 152 connected to sense amplifier 14 is collectively controlled by column decoder 13.
An output of an X predecoder 8 and an output of a Y predecoder 9 in FIG. 7 are applied to row decoder 12 and column decoder 13, respectively.
Referring again to FIG. 7, an X address buffer 6 is controlled by a control circuit 11 so as to buffer external address signals .phi.1-.phi.n to apply the same to X predecoder 8. A Y address buffer 7 is controlled by control circuit 11 so as to buffer external address signals .phi.1-.phi.n to apply the same to Y predecoder 9 and an address change detecting circuit 10.
X predecoder 8 decodes the address signals from X address buffer 6 and supplies these decoded signals to row decoder 12 within each of blocks 101-108. Y predecoder 9 decodes the address signals from Y address buffer 7 and supplies the decoded signals to column decoder 13 (see FIG. 8) within each of blocks 101-108.
In data writing and data reading, external address signals .phi.1-.phi.n are set such that one of output signals of row decoder 12 and one of output signals of column decoder 13 in only one block are at a high level and that all of output signals of row decoder 12 and column decoder 13 in the other blocks are at a low level.
Therefore, in any of the blocks (see FIG. 8), row decoder 12 further decodes the signals from X predecoder 8, and supplies a power supply potential Vcc corresponding to a high level only to one of word lines WL, and a ground potential corresponding to a low level to all the other word lines WL. This enables data writing and data reading to/from each memory cell MC connected to the word line WL.
If a potential of one word line WL is higher than a threshold voltage of transistor Tr in memory cell MC, the transistor Tr in each memory cell MC connected to the word line WL turns on and electrically connects capacitor C to a bit line BL1 or BL2 connected to memory cell MC. Therefore, if a potential of bit line BL1 or BL2 is high, capacitor C is charged and data "1" is written into memory cell MC. Conversely, if the potential of bit line BL1 or BL2 is low, capacitor C is not charged and data "0" is written into the memory cell MC.
Data writing is carried out by forcing bit line BL1 or BL2 to have a potential corresponding to an external write data Din. More specifically, in data writing, each sense amplifier 14 applies two signals from transfer gate 15 to two corresponding bit lines BL1, BL2, respectively.
If bit line BL1, BL2 are not forced to have such a potential, transistor Tr turns on. Therefore, when capacitor C is charged, a potential rise of bit line BL1 or BL2 connected to the transistor Tr occurs and when capacitor C is discharged, a potential fall occurs. As a result, a small potential difference is produced between two bit lines BL1, BL2 forming bit line pair BL. Data reading is then carried out by detecting and extracting the potential difference between bit lines BL1 and BL2. More specifically, in data reading, each sense amplifier 14 senses and amplifies the potential difference between two corresponding bit lines BL1, BL2 and applies two signals having complementary potentials to transfer gate 15.
Column decoder 13 further decodes the signal from Y predecoder 9 so as to apply a potential of a high level to gates of only two transistors of transistors 151, 152 in transfer gate 15 which are connected to one of sense amplifiers 14 and a potential of a low level to the gates of all the other transistors. As a result, only two transistors 151,152 connected to the sense amplifier 14 turn on and only this sense amplifier 14 is electrically connected to IO line pair 2.
IO lines 201 and 202 are forced to have complementary potentials corresponding to external data signal Din in data writing. In data reading, potentials of IO lines 201 and 202 are supplied to IO circuit 16 in FIG. 7 as one read data signal.
Therefore, in data writing, an external data signal is written into one memory cell MC connected to one word line WL having a potential of a high level (hereinafter referred to as a selected word line) and either of two bit lines (hereinafter referred to as selected bit lines) BL1, BL2 corresponding to one sense amplifier 14 connected to transistor pair 500 which are in an on-state.
In data reading, a potential difference between selected bit lines BL1 and BL2 produced by a stored data of one memory cell MC (hereinafter referred to as a selected memory cell) connected to the selected word line WL and the selected bit line BL1 or BL2 is amplified by sense amplifier 14 and appears between IO lines 201 and 202.
Therefore, in data writing, an external data is written into only one of the blocks, and in data reading, a data is read from only one of the blocks. By appropriately changing address signals .phi.1-.phi.n, data writing and data reading can be carried out from/in a desired block to a memory cell at the desired location.
As shown in FIG. 7, corresponding to each of blocks 101-108, an equalizing circuit 4 and a pre-amplifier 3 are provided.
As shown in FIG. 8, both equalizing circuit 4 and pre-amplifier 3 are connected to IO lines 201, 202 of a corresponding block.
Each amplifier 3 is controlled by address change detecting circuit 10 so that, in data writing, it amplifies a signal supplied from IO circuit 16 and supplies complementary potentials to IO lines 201 and 202 of a corresponding block, and that, in data reading, it further amplifies a potential difference between IO lines 201 and 202 of the corresponding block and supplies the amplified difference to IO circuit 16.
Each equalizing circuit 4 is controlled by an equalization control signal generating circuit 5 so that, every time external address signals .phi.1-.phi.n change, IO lines 201 and 202 of the corresponding block are forced to have an equal potential.
IO circuit 16 is controlled by a control circuit 11 so that, in data writing, a signal corresponding to external write data Din is supplied to each pre-amplifier 3 and, in data reading, a signal from each pre-amplifier 3 is applied to an external terminal as a read data Dout.
Address change detecting circuit 10 detects the change of the address signals from an Y address buffer 7 and outputs a detection signal to all of pre-amplifiers 3 and equalization control signal generating circuit 5.
Each pre-amplifier 3 is activated in response to the detection signal. Equalization control signal generating circuit 5 is controlled by control circuit 11 such that, in data writing and data reading, circuit 5 generates equalization control signals EQ for activating equalizing circuit 4 in response to the detection signal. These equalization control signal EQ are commonly applied to all equalizing circuit 4. Therefore, whenever the next memory cell into which and from which data is to be written and to be read is selected, then each IO line pair 2 is equalized.
FIG. 9 is a circuit diagram showing a configuration of equalizing circuit 4. In FIG. 9, a configuration of one equalizing circuit is shown as a representative.
Referring to FIG. 9, each equalizing circuit 4 includes an N channel MOS transistor 40 connected between IO lines 201 and 202 of a corresponding block and receiving equalization control signal EQ at the gate. In each of data reading and data writing, whenever external address signals .phi.1-.phi.n change, equalization control signal EQ attains a high level. As a result, transistor 40 is turned on, data line 201 and data line 202 are electrically connected, and therefore these data lines 201, 202 have an equal potential.
Such equalization of IO lines is carried out in order that, when data is successively read from two different memory cells, for example, even if the levels of potentials of paired data lines 201 and 202, which are determined by the previously read data from one memory cell is opposite to a level corresponding to a stored data in a memory cell from which data is to be read, a proper potential appears rapidly and securely on IO lines 201 and 202 in the data reading.
Control circuit 11 controls a predetermined circuit portion such that, in response to an external control signal such as a low active, row address strobe signal RAS, a column address strobe signal CAS, a write enable signal WE, and an output enable signal OE and the like, a circuit operation for data writing, circuit operation for data reading, or a state in which neither data writing nor data reading is carried out (hereinafter referred to as an off time or a standby state) is achieved.
Row active signals will be hereinbelow marked with /.
Referring to FIGS. 7 through 10, a circuit operation of data reading in the DRAM will be described in more detail.
FIG. 10 is a timing chart showing potential changes of main control signals and signal lines in data reading.
In this description, it is assumed that data is successively read out from a plurality of memory cells in the same row in the same block.
First, a row address strobe signal/RAS (FIG. 10A(a)) is lowered with external address signals .phi.1-.phi.n (FIG. 10(b)) indicating an address A1 supplied.
In response to the fall of row address strobe signal /RAS, X address buffer 6 operates, and, in one of the blocks 101-108 constituting memory cell array 1, a potential of one of word lines WL is raised to a high level, as shown in FIG. 10(c), by row decoder 12.
If a memory cell MC connected to the selected word line WL is connected to bit line BL1, as shown in FIG. 10(d), in response to the rise, each potential of bit lines BL1 slightly rises or falls depending on the stored data in the memory cell MC connected to the selected word line and the bit line BL1. Meanwhile each bit line BL2 does not change.
Conversely, if memory cell MC connected to the selected word line is connected to bit line BL2, in response to the rise, a slight potential rise or a slight potential fall occurs on each bit line BL2 depending on a stored data in one memory cell MC connected to the selected word line WL and the bit line BL2. Meanwhile, a potential of each bit line BL1 does not change.
Each sense amplifier 14 increases a slight potential difference produced as described above between bit lines BL1 and BL2 forming corresponding bit line pair BL to a magnitude of v as shown in FIG. 10(d). As a result, a potential of each bit line BL1 and a potential of bit line BL2 paired with the bit line BL1 are at complementary logic levels.
At the time when the potential difference between paired bit line BL1 and bit line BL2 is increased to a certain degree by a corresponding sense amplifier 14, Y address buffer 7 operates. As a result, a potential of any of output signal lines (hereinafter referred to as column selection lines) CSL of column decoder 13 of one block attains a high level, as shown in FIG. 10(e), at the time when the potential difference between paired bit line BL1 and BL2 is increased to the certain degree.
Therefore, depending on the potential of selected bit lines BL1 and BL2, potentials of data lines 201 and 202 change complementarily in response to the rise of the potential of the column selection line, as shown in FIG. 10(f).
That is, when the potential of selected bit line BL1 is at a high level, potentials of data lines 201 and 202 start to rise or fall, respectively, in response to the rise of the potential of the column selection line CSL. Conversely, if the potential of selected bit line BL1 is at a low level, potentials of IO lines 201 and 202 start to fall and rise, respectively, in response to the rise of the potential of column selection line CLS.
Thus, at the time when the potential difference between IO lines 201 and 202 is sufficiently increased, IO circuit 16 operates. As a result, the potential change on IO line pair 2, that is, stored data of the memory cell selected by address A1 is externally output without fail as a data signal of a logic value corresponding to the potential change.
External address signals .phi.1-.phi.n are changed to signals indicating an address A2 in which a potential of a column selection line different from the one selected previously attains a high level.
Since the address change is detected by address change detection circuit 10, in response to the address change, as shown in FIG. 10(g), an equalization controlling signal EQ maintains a high level only in a ceratin period .tau..
A change timing of external address signals .phi.1-.phi.n is set so that equalization controlling signal EQ attains a high level after the potential difference between data lines 201 and 202 in the block from which data is read reaches the maximum value.
In the period when equalization controlling signal EQ is at a high level, IO lines 201 and 202 are electrically connected in each of blocks 101-108. As a result, in a block from which data is read, a potential of IO line 201 (or 202) which has risen and a potential of data line 202 (or 201) which has fallen start to fall and rise, respectively, in response to the rise of equalization controlling signal EQ, and eventually equalized to an intermediate potential Vcc/2 between power supply potential Vcc and a ground potential 0V (hereinafter referred to as an equalization potential).
In response to the change of external address signals .phi.1-.phi.n, a potential of column selection line CSL different from the previous one attains a high level in the block from which data was previously read. As a result, depending on respective potentials of two bit lines BL1 and BL2 different from the previous ones, potentials of IO lines 201 and 202 start to change from the equalization potential as shown in FIG. 10(f).
When equalization controlling signal EQ is at a high level, the length of period .tau. is set such that before a potential of one column selection line CSL attains a high level, equalization controlling signal EQ falls to a low level. Therefore, by the circuit operation described above, stored data of one memory cell MC selected by address A2 is also supplied to a pre-amplifier 3 through sense amplifier 14 connected to selected bit line pair BL, transfer gate 15 and IO line pair 2.
As described above, in data reading, whenever external address signals .phi.1-.phi.n are changed, equalization of data lines 201 and 202 in each block, release of the equalization in each block, signal transmission from one bit line pair BL to data line pair 2 in response to a rise of a potential of one column selection line CSL in one block are repeated.
In a semiconductor memory device having a memory cell array divided into blocks, original functions of the semiconductor memory device such as data writing and data reading are activated only in a particular block indicated by external address signals. Since none of the blocks except the particular block operates, power is scarcely consumed. Therefore, power consumption is reduced in operation of the semiconductor memory device.
An activated block will be hereinafter referred to as a block of a selected state. In a block of a non-selected state, IO lines 201 and 202 are not electrically connected to any of bit lines BL1, BL2, so that, as shown in FIG. 10(h), the IO lines are held at the equalization potential independent of a change of a potential level of equalization controlling signal EQ (FIG. 10(i)).
Although, the number of blocks of a selected state is 1 in the above description, the number may be more than one. In such a case, in data reading, data is read respectively from these plural blocks, and, in data writing, data is written into these plural blocks respectively.
As described above, in a conventional DRAM divided into blocks, an equalizing circuit for equalizing a data line is provided corresponding to each block, that is, corresponding to each IO line pair, and all equalizing circuits are controlled collectively by the same equalization controlling signal. As a result, in data reading, also in each of the blocks except the block of a selected state (hereinafter referred to as blocks of a non-selected state), equalization of a data line and release of the equalization are carried out.
That is, referring to FIGS. 7 through 10, in data reading, whenever external address signals .phi.1-.phi.n change, equalization controlling signal EQ supplied to each equalization circuit 4 rises to a high level and then falls to a low level after a certain period .tau.. Therefore, in each of 8 blocks 101-108, whenever external address signals .phi.1-.phi.n change, data lines 201 and 202 are electrically connected for the certain period of time, and then electrically cut off.
Such control of electrical connection state of data lines 201 and 202 in each block is performed by applying equalization controlling signal EQ to a gate of transistor 40 in equalizing circuit 4 corresponding to the block. A gate electrode of a MOS transistor is formed of polysilicon or the like on a semiconductor substrate with an insulating film interposed, so that a change of a potential applied to the gate of the MOS transistor causes charge/discharge current of a magnitude corresponding to a gate capacity to be generated at the gate.
Therefore, the charge/discharge current for charging/discharging the gate flows between the gate of transistor 40 in each equalizing circuit 4 and equalization control signal generating circuit 5.
When the gate capacity of transistor 40, potentials respectively corresponding to a high level and a low level of equalization control signal EQ, a period of a change of enteral address signals .phi.1-.phi.n and the number of times of changes of external address signals .phi.1-.phi.n in one read cycle (a period in which row address strobe signal/RAS falls to a low level and then recovers to a high level) are respectively represented as CG, VH and VL, tc, and N, and the number of blocks as B, a total current I generated in response to equalization control signal EQ in equalizing circuit 4 during one read cycle can be calculated by the following expression. EQU I[(CG.times..vertline.VH-VL.vertline..times.B) / tc].times.N
For example, if CG, VH, VL and tc are 0.4pF, 5V, 0V, 40ns, and 2 which are typical values, current I is (0.1mA.times.B).
The number of blocks in a memory cell array, that is the number of blocks B has been increasing in order to meet the demand of less power consumption and higher speed operation, as the number of the memory cells in each block increases due to recently advanced semiconductor memory device having higher integration density. That is, in FIG. 7, memory cell array 1 is divided into only 8 blocks, but these days a memory cell array is frequently divided into more blocks. For example, if the number of blocks B is 100, current I reaches 10mA.
In operation, the semiconductor memory device consumes current in many circuits other than such equalizing circuits. 10mA corresponds to a relatively large amount compared to consumed current in the whole semiconductor memory device.
Therefore, as the number of blocks increases, charge/discharge current of an equalizing circuit becomes too large to neglect as consumed current in operation of a semiconductor memory device and can be an important factor to increase power consumption in the semiconductor memory device. That is to say, charge/discharge current of an equalizing circuit produces a phenomenon which runs counter to a recent demand of less power consumption of a semiconductor memory device.